Reverse engineering the Amstrad CPC Revision Zero PCB made me wonder exactly what a 6502 based Amstrad would look like. So I have begin a project, which I’m calling the CPC ZERO, to design such a machine.

The prototype PCB is so broken that it doesn’t give much of a starting point for a system, so my intention is to use the highest level of design choices which they made with the Zero and add in a bunch of design choices from the actual CPC464. Basically I’ll be using the key ‘large’ chips – processor (obviously), 6845, AY-3-8912 and 8255 – and designing around those. If I get as far as creating a PCB then I’ll use a layout inspired by that of the prototype.

In short my goals for the project are:

• A 6502 running at 2MHz. Many home computers ran the 6502 at 1MHz but the BBC micro was already clocking it at 2MHz a couple of years before the Amstrad was released. I would feel lazy not to copy that on the CPC. Clocking the CPU at 2MHz also creates some ‘interesting’ challenges with regards to memory access.
• Video modes similar to those of the CPC, ie. 80 column text and a good range of colours. I’m not sure if 80 column text was specified by Amstrad or by those who eventually designed the system but there seems to have been a desire to create a machine which was suitable for both games and business use and business use pretty much requires high resolution text.
• To use period appropriate hardware. I want to create a machine which could have been designed at the time so I’ll be using 74LS series logic and DRAM memory. This also means I’ll be solving period appropriate design challenges. I will, however, be using a 65C02 CPU – because I have one in the parts box – and EEPROM – because it’s much easier to reprogram. I don’t think either of those makes a material difference to the project.
• To blog the entire process in detail. There’s a fair bit of content out there using an 8-bit processor with modern SRAM and a serial port and an occasionally piece which adds simplistic video output but there’s little about ‘real world’ video, memory contention and sequencing so I hope this project can fill that hole.

Prototype Build System

As for how to prototype the design there are four main options:

• Breadboards. I’ve built large-ish breadboard projects before (such as the Ben Eater TTL computer) and they’re a nightmare once you get beyond half a dozen boards. The key issues being the ease with which wires can get accidentally removed, and the resistance, signal transmission, power distribution of the board to board connections. They’re a hard no for me on such a large project.
• PCBs. These are fairly quick to design and have manufactured. However I want to iterate the project slowly through each stage and document as I go which might require up to a dozen revisions. A PCB the size of the original CPC464 would cost over $50 per board¹. Using PCBs would also entail repeatedly soldering up the early parts of the design which just feels tedious.
• Modular PCBs. I could design each stage as a module and connect them all together. Past experience tells me that getting connector pinouts correct is difficult even if you know what needs to be connected. In any case I’ll be modifying earlier stages as later ones are added which negates much of the modular benefit anyway.
• Wire wrapping. This is a period appropriate method for prototyping electronics, and a technique which I’ve never done it before so it will be an interesting learning experience. True wire wrapping sockets are expensive so I’ll have to tweak the method to be more wallet friendly but that will also be interest. The collected opinion of The Internet is that wire wrap should give similar build times to breadboards plus the reliability close to that of a PCB. There are concerns about signal integrity at high frequency but this project should be slow enough to avoid them.

So, wire wrapping it is then.

Part Zero Design

Onto the first stage of the design which can be seen in the schematic above. It’s the most basic circuit needed to get a 6502 operating: CPU and ROM and glue logic.

The 6502’s RWB² is low when the CPU is writing (to memory or I/O) and high at all other times. I’m inverting it and connecting to the /OE (output enable) input of the ROM. /WE is fixed high and /CS fixed low. Thus the ROM is writing to the bus at all times except when the CPU is writing.

The RDY pin of the 6502 is both input and output so needs a pull-up resistor to 5V. The other inputs can be connected directly to 5V except for PHI2IN (the clock) and /RES (reset).

U4 is a ‘574 latch driving a set of LEDs. In a later revision I’ll drive this from an I/O port to use as a quick and easy status output to test the CPU. For now I have connecting it’s clock (latch) input to the CPUs PHI1OUT signal. PHI1OUT is inverted PHI2IN. Using it in this way means the LEDs will latch whatever is on the bus at each processor cycle and should show if the processor is running code.

The Build

I’ll talk more about my wire wrapping technique later once I’ve ironed out any teething troubles. For now here are photos on the front and rear of the board so far.

The ROM contains whatever was in there from the last project I used it on. I think it was probably some revision of the Amstrad firmware so I feels appropriate for the CPC ZERO to begin life running Amstrad software, even if that software is for a Z80!

For clock and reset I’m using an old board from another project. One of the first PCBs I designed and which has a few ‘quirks’ but which allows be to pause, single step and slow clock the ZERO.

You can’t tell from a still photo, but the LEDs are showing fresh data on each clock cycle. That doesn’t prove every connection is correct but does show the CPU is clocking the address pins which is good enough for this stage.

Links

The repository for the build can be found below. I’ll be updating as the build goes along so it may look a little different to the schematics above.

https://github.com/Bread80/CPC_ZERO

Footnotes

1. Of course you get multiple boards for your money but I’ll only be needing one of each revision so that is, effectively, a per board price.
2. Or R/W where the W is inverted. Thus the name Read-Write-Bar.