Designing an Intel 8008 Computer. Part 1: Power, Clocks and Signals

The Intel 8008 was the second microprocessor, and the first 8-bit one1, as well as being the first microprocessor to go on general sale. It’s an interesting and quirky beast which was constrained by bleeding edge technology and a curious edict from the Intel management.

In terms of history, the 8008 was designed under contract from Datapoint (then called CTC – Computer Terminal Corporation) as a single chip version of their Datapoint 2200 computer. This was a desktop computer (the world’s first) with a TTL processor made from approximately 150 discreet logic chips. Thus the instruction set was specified by Datapoint to match that of the 2200 (but with a few additional instructions).

I’m not sure who specified the hardware interface – Intel or Datapoint – but Intel management at the time would only allow chips to be designed using small packages (i.e. with a small number of pins). Thus the 8008 is in an 18-pin package (and the designers had to fight to get the limit upped from 16), which meant that the data pins had to be ‘triple-plexed’ between address high, address low and data, and other signals had to be encoded onto the pins that where left. All of which meant that the chip needed a fair few external chips to get up and running.

For a chip with such an important place in history there is a distinct lack of information about it available on the internet. Indeed, the only schematics I can find are those in the datasheet (rev 1, and rev 2). While the chip is designed to be compatible with standard TTL signal levels the design in the datasheet uses a number of Intel specific support chips, which would be difficult to source and for which, again, there is very little information available.

I’ve been building a breadboard computer based around the 8008, which I later intent to turn into a PCB, and in these articles I’ll be writing about my experiences with it, the schematics I’ve used and the many quirks of the chip and how to work with (and around!) them. This is an unashamedly deep dive which I hope will form a definitive reference to the 8008.

In this first article I’ll get as far as getting the chip to clock and process instructions (but note that attaching a ROM to feed in an actual program will have to wait).

Fig 1. Intel 8008 Pinout (from datasheet)
Fig 1. Intel 8008 Pinout (from datasheet)

The Power Supply

The 8008 requires a 14V power supply. However, to make it easier to integrate with TTL logic chips Intel actually specify this as +5V and -9V power connections. I’m not very confident with power supply design, but Matts Engstrom – @matsEnstrom – was kind enough to suggest as circuit which I have used as a basis for the following.

Fig 2. Power input schematic
Fig 2. Power input schematic

The Clock Signals

The 8008 uses a two phase clock signal which includes both minimum and maximum timing requirements. Also note that the phasing between the two signals is not symmetrical.

There is a faster variant of the 8008 designated the 8008-1. These where from the same production line as the 8008 and were simply chips able to run at a slightly faster speed. The 8008 runs at a maximum clock speed of 500KHz, the 8008-1 at a maximum of 800kHz.

This first diagram shows the clock timing requirements for the 8008.

Fig 3. 8008 clock timing requirements. Times in uS
Fig 3. 8008 clock timing requirements. Times in uS

Note that if you ran every part of the cycle at the minimums (top of the diagram) you would exceed the minimum for the combined timings (bottom of the diagram). This actually gives us some flexibility in which part of the cycles to stretch. My chosen variant is as follows.

Fig 4. Suggested 8008 clock timings
Fig 4. Suggested 8008 clock timings

I’ve also added to that diagram the times in multiples of a 20MHz clock, i.e. the number of 20MHz (50nS) cycles to hold each state. This will be helpful if dividing down a 20MHz signal to generate the clocks.

Moving on the the 8008-1, here is the timing requirements from the datasheet.

Fig 5. 8008-1 clock timing requirements. Times in uS.
Fig 5. 8008-1 clock timing requirements. Times in uS.

The 8008-1 is fast enough that there is no need to stretch any cycles, and the minimums can be used throughout. Note that the maximums are the same as for a base 8008 which means we can use the same timings as an 8008 if we’re happy to sacrifice some speed. These timings are also flexible enough that you could run every stage of the cycle at 0.35uS and use a much simpler timing circuit with roughly a 10% performance penalty.

The next diagram shows these timings translated to multiples of 20MHz.

Fig 6. 8008-1 clock timings showing 50nS multiples.
Fig 6. 8008-1 clock timings showing 50nS multiples.

Generating Clocks with a Pico

At this stage I’m generating the clock signals using a Raspberry Pi Pico. This enables me to get up and running quickly and with clock signals which I can easily tweak if needed. I’ll return to create a TTL based circuit later in the project.

I’m using PWMs to generate the clocks and the Pico has ample power to generate both 8008 and 8008-1 clocks simultaneously on separate pins.

Signal Decoding, Processor Cycles and T-states

The first layer of decoding what our computer needs to do involves the four status signals, SYNC, S0, S1, and S2.

S0 to S2 encode the processor state as per the diagram below. The are properly described as the state control coding.

Fig 7. State Control Coding
Fig 7. State Control Coding

And the diagram below shows how the state signals combine with the SYNC signal and the clock.

Fig 8. Instruction Cycle
Fig 8. Instruction Cycle

To understand this lot we need a brief diversion into how processors operate.

Basics of Processor Operation

Processor use something called a ‘fetch execute cycle’, sometimes referred to as a ‘fetch, decode, execute’ cycle. This relates to the way that a processor has to read (fetch) and instruction from (usually) memory, decode the instruction, and then execute some operation(s) dependent on that instruction.

The fetch part of the cycle can be further broken down into:

  • output an address (i.e. the program counter) for the instruction to be read from.
  • read back the instruction from memory.

During the execution phase an instruction may need to read (or write) one or more additional bytes of data. Examples of this are:

  • Reading an inline data byte from the memory address following the instruction.
  • Reading (or writing) a byte from a memory address specified by (e.g.) a register.
  • Reading an inline destination address for a jump or subroutine call.

In this last case the processor needs to read two bytes after reading the instruction byte.

Each of these memory cycles is similar to the fetch operation – output an address, then read (or write) a byte at that address. In Z802 speak these memory cycles are called M1 cycles, and I’ll use that term here for clarity, even though it isn’t officially part of the 8008 vocabulary.

Thus a jump instruction involves three M-cycles: one to read the instruction and two more to read the two byte address.

These M-cycles are further broken down into T-states. A T-state represents a single step in within an M-cycles. Thus an M-cycle could involve the following T-states:

  • output address
  • read data (from the output address)
  • process data (i.e. store it into a register, as specified by the instruction).

Processor Cycles on the 8008

We can now turn to the 8008 to see how this all works out in practice. With reference to the Instruction Timing Diagram above a typical M cycle (a.k.a. processor cycle) on the 8008 consists of the following T-states:

  • T1 – Output the low 8-bits of the address.
  • T2 – Output the high 6-bits of the address (plus two control bits – ignore these for now).
  • T3 – Read instruction or data, or output data to be written
  • T4 – Instruction execution (Optional depending on the instruction)
  • T5 – Instruction execution (Optional depending on the instruction)

The following states are also possible:

  • T1I – If an interrupt has been raised the processor will execute a T1I cycle instead of a T1. This will be followed by a regular T2 thru T5 cycle.
  • STOPPED – If the processor executes a HALT instruction it will enter the STOPPED state and remain there until an interrupt is generated.
  • WAIT – The 8008 can be stopped during a T3 state – i.e. when reading or writing data – by taking the READY input low. The WAIT state acknowledges that input and is maintained until the READY signal returns high.

The SYNC signal, along with the clocks, can be used to accurately time external operations.

State Control Decoding

Turning to a practical design for a computer we can use a 74138 (a.k.a. ‘138) to decode the S0 to S2 lines into eight separate signals.

Fig 9. State Control Decoding Schematic
Fig 9. State Control Decoding Schematic

That’s warmed us up with some basics of the 8008 which we will build on in the next article. This will deal with how to start the processor running, which requires us to understand how the interrupts work, as well as adding a single stepping ability using the READY (/WAIT) signal.

Footnotes

  1. This article from Ken Shirriff suggests it was pipped to the post by the TMX1795, although that one was never put into production.
  2. On the Z80 not all M-cycles include a memory access, some are used purely for internal operations.

Leave a Reply

Your email address will not be published. Required fields are marked *