I think the genesis of the Amstrad CPC is fairly well known among retro enthusiasts: Amstrad hired some guys to design a machine based around the MOS 6502 processor, but the task was beyond them, Alan Sugar said “You’re Fired”, and a new team, headed by Roland Perry, were hired and came up the the design we know and love.
I’d always thought that was the end of the story, but last year Roland Perry took a prototype PCB of the ‘Revision Zero‘ computer to a retro meetup and Deepfb was good enough to take some photos to share with the rest of us.
This raises an interesting question: is it possible the rescue the design and get it up and running? Before you get your hopes up, the answer is a resounding ‘No’. What they created was not merely bad, but so bad that it’s unfixable. But it should still be interesting to reverse engineer what the did and gasp at everything they messed up.
General Layout
I’ll start with a tour of the PCB to get you oriented. I’ve added extra annotations to the hand-written originals on the board. The layout clearly resembles the final CPC design. That’s because Amstrad had already designed the case and keyboard.
The connectors are pretty much what we’re used to. Working clockwise from the left we have the keyboard connector, audio out, joystick (“Games”), printer, expansion, 5V power in, RGB video out, and the ‘tape’ connector which also connects to the power switch and on board speaker. There’s also an unlabeled connector between the expansion port and power jack which I can’t establish a purpose for. Possibly this was intended to be composite video out, but composite would be a two pin connector and this footprint looks like that of the TRS audio jack.
The Silicon
Moving to the silicon, most of the larger chips are missing but if take a guess that the final machine used the same or similar parts, and the footprint appear to bear that out. On that basis we it’s possible to identify the 6502 with the 27256 (32kB) ROM above it.
To the left of that is the 8255 PIO and then the AY sound generator. The final CPC used an AY-3-8912 whereas this is the more expensive 40-pin AY-3-8910 part. These are very similar with the -8910 variant adding a second parallel port to the -8912’s single one. The other large chip, to the right, is present on the board and it’s a 6845 video controller.
The Smaller Chips
Moving on to the smaller chip, and a few of these are also not present. It’s not easy to tell if they were to be standard logic parts or something programmable like the HAL used in the 6128.
To the left of the sound chip is a 74LS138 3-to-8 decoder generating keyboard row select1 signals.
Below the 8255 is an LM258 dual op-amp processing tape input and/or output signals.
The block to the right of the CPU has a lot of chips missing, but there’s eight missing chips and the traces to them look like what I’d expect to see on 4164 DRAMs. Either side of these are a pair of 74LS257 2-to-1 multiplexers which are probably handling RAM address selection between RAS and CAS (upper/lower chip) and between CPU and video (left/right pairs).
The block above the RAM is probably doing port decoding and generating chip select signals. To the right of that is a missing chip and 74LS245 bus transceiver. These probably constitute the bus connections between the CPU data bus and the video data bus.
The chips to the right of the 6845 are roughly divided into an upper block and a lower block with very few traces between them. The upper block connects to the RGB port so probably handles pixel decoding and video timing. The block to the left includes a timing crystal and probably handles sequencing of signals to the rest of the machine.
The X-Ray Image
Having just gotten you orientated to the layout in landscape I’m now going to rotate the board 90 degrees. I apologise for any confusion, but this is the image I originally annotated when trying to reverse engineer the board. Annotations include adding reference designators to the ICs which will make them easier to discuss. I’ll use cropped versions of this in the discussion below.
The image itself is the the ‘x-ray’ image created by CPCWiki user Deepfb by merging the photos of the top side and underside of the board. Its not possible to see the traces on the top side of the board which are underneath chips, and there are some parallax issues especially near the ends of the board, but it’s good enough for our purposes here.
Reverse Engineering
Now lets go over the board for a detailed look at what they did.
The CPU
The CPU seems like a logical place to start. Comparing the 6502 pinout with the PCB we see the address and data lines have traces attached, however the control signals have none apart from a link between what appears to be pin 2 and pin 382. There’s no clock connection (PHI0) and nothing connected to the R/W pin (read/write) – which is required for memory and I/O to function.
So my first conclusion is that there is no way the 6502 will run. Maybe they were planning to bodge wire these on later? We’ll see.
ROM and Address Decoding.
Zooming out to show the CPU, the ROM and part of the multiplexer and I/O decoding blocks.
They’ve done a good job of wiring address and data traces to the ROM. This looks like a promising start.
Moving down to some of the the address decoding logic. U41 is an ‘LS27 triple three input OR gate which we can see has multiple connections to CPU address lines. U42 is an ‘LS1383 3-to-8 decoder. When not enabled (G1, /G2A, /G2B) this chip sets all it’s outputs (Yn) high. When enabled it will take one output low depending on the three select input lines (A, B, C). For I/O decoding I would expect to see the enable and select inputs connected to address lines, probably via other logic gates4, and the outputs connected to chips such as the 8255 and 6845.
What we actually see is that three of the output lines (pins 12, 13, 14) are connected to data bus lines (pins 11, 12, 13 of the ROM equating to D0, D1 and D2). Not only that but pin 12 is also connected to address line A11 (pin 20 of the CPU). So they’ve permanently shorted an address and data line and an output from U42. Needless to say this is not ideal.
Let’s give them the benefit of the doubt and suggest that they accidentally rotated U42 by 180 degrees, and A11 was intended to connect to some of the select lines while the three data lines connected to the enable pins. It appears as though S0 (pin 9 on the PCB) is connected to ground. If so the address lines on /G2A and /G2B would be able to activate outputs Y0, Y2, Y4 or Y6. However the only traces running from the outputs of the (now rotated) chip appear to be Y4, Y5 and Y6.
I shall discretely move on to the RAM and multiplexers.
RAM and Multiplexers
Each pair of ‘257 multiplexers should (probably) be forwarding either A0 through A7, or A8 through A15 to the 4164 DRAMs. The pair at the top should be enabled when the CPU needs to access RAM, the pair at the bottom when the 6845 needs them. The selection between address high or address low is done via the A/B pins. The enabling (or disabling) of a pair is done with the /G inputs.
On U39 and U40 (at the CPU end) we can see that the pairs of A/B and /G pins are correctly routed together but neither signal appears to be connected any further. The other pair is even worse with, as best I can see, no connections to any of these pins.
Bus Interconnects
Zooming out a little to show the entire area between the CPU and ROM, at the top, and 6845 at the bottom. DRAM and multiplexers are on the left, I/O decoding in the block at top-right. In the bottom-right are U25 and U28 which are probably intended to allow data to flow between the the CPU data bus and video data bus (similar function to IC114 and IC115 in a CPC).
The traces running leftwards in an S-shape from U25 are the data lines to the DI and DO (Data in and Data out) of the RAMs. The traces running downwards connect to the 6845 and (probably) also send video data to the pixel decoder circuit. But look at the PCB and you’ll note a lack of traces running up from these to the CPU and ROM. The three data lines I mentioned earlier between the ROM and U42 don’t appear to run any further, and all the other traces in that area are address lines.
Expansion Connector
While I’m in the area I’ll discuss the expansion connector. It’s hard to see on the x-ray image, but all the pins on the underside are connected to the ground trace which runs vertically through them. This leaves only 17 pins on the top side for signals (contrast this to the CPC’s expansion connector which has 47 signal lines on a 50-pin connector).
Of those 17 pins only twelve are connected to anything, and one of those just runs to a via with nothing beyond. The eleven remaining traces all appear to connect to data lines on U25 or U28. Granted I haven’t traced exactly where they go, and the top two lines do head upwards into the other logic. So perhaps they’re doing something useful and there’s only nine data lines on the connector…
The 6845 CRTC
The MC6845 CRTC (cathode ray tube controller) is essentially a set of counters driving the address (MAn and RAn) and the VSYNC, HSYNC and DISPEN (display enable) outputs which can be used to generate video timing signals.
The PCB appears the have the data bus connected correctly, and there are traces to the Enable and R/W pins 22 and 23. On the output side traces run between address lines and the multiplexers, however /CS on pin 25 is connected to MA13 on pin 17, MA12 connects to pin 11 of U18 despite both of these being outputs. A trace runs south from DISPEN which could well be correct but HSYNC and VSYNC either connect to the multiplexers of nothing.
Perhaps this could also be another case of the footprint being rotated or mirrored somehow but, as mentioned, they have the data bus on the correct pins. And at this stage battling to make to make sense of what has happened would not help my sanity.
Sequencing Logic
I actually spent far to long trying to reverse engineer the sequencer logic. At the top is the crystal and just below it a LS04 hex inverter. This is probably correctly outputting a clock signal on pin 8. The rest of it is hard to examine with traces hidden under the chips but there are enough outputs connected to outputs to tell me this is not worth looking at in any detail.
What I can see is an ‘LS163 four bit counter and ‘LS138 3-to-8 decoder which may have been intended to sequence the various steps of a system cycle, and there are plenty or ‘LS112 J-K flip flops for storing state.
Video Output
I’m not even going to try and reverse engineer the video generation circuit. Also I’m not an expert at video signals but I do know they don’t run at TTL signal levels and require some analogue circuitry to work properly (for example, as shown on the CPC464 schematic). There’s none of that on the PCB, the TTL outputs being connected directly to the DIN socket.
Keyboard
Moving to the other end of the board to look at the keyboard connections around the AY-3-8910. The final CPC design (as shown above) uses an ‘LS145 to activate one of ten row select lines (Y1 to Y10), and the column data (X1 to X85) is read back via the parallel port on the AY.
The design on this PCB design uses an ‘LS138 to select one of eight columns with the keyboard data returned on the ten row inputs. Flipping the design this way requires ten input lines and, therefore, the use of both the -8910’s parallel ports. This is a workable design but the need to poll both ports would slow down the keyboard scanning process.
Another issue here is the use of an ‘LS138 to generate the column select. The LS145 used on the CPC has open collector outputs – which effectively means that only the selected output is sending a signal. The ‘138 has bipolar outputs which are always outputting. This has necessitated the use of (what I assume are) diodes to prevent short circuits.
This part of the design probably works but is definitely sub-optimal.
Audio
Staying with the sound chip I’ll look at the audio output. The Amstrad here some analogue circuitry to mix the three channel outputs from the AY to give both a stereo signal to the output jack and a mono mix to the internal speaker. The resistors on the Rev 0 design appear to be pull-ups for the I/O ports so I’m not sure what they’ve done with the audio signals. Indeed the two lines from the audio jack appear to end short of the chip.
The Parallel and Games Ports
The AY-3 family of chips are not directly compatible with the Z80 (or indeed the 6502), therefore both the CPC and Revision 0 use the 8255 to interface between them. Here we can see the 8255 parallel port connecting to the AY, and also to the parallel port. I’m not convinced that using the same lines for both the AY and parallel port is a great idea but it may have worked in practice.
What probably would not have worked is the lack of control and handshaking lines to the port. The CPC uses an 8-bit latch to drive the parallel port with bit 7 used for handshaking (thus leaving only seven bits for data – a cost cutting measure which caused much criticism back in the day). The same could also be happening here but the double use of the lines makes that unlikely to work.
Also connected to the 8255 is the games (joystick) port. You can play with this one in your own time if you fancy.
Tape I/O
Finally, for completeness, the tape in and out signals which are routed to/from the 8255 to the internal connector via U45, via the LM258 op-amp as mentioned earlier. They appear to be connected to the /WR and RESET pins on the 8255 :shrug:. The stereo mix to the internal speaker runs through this area on it’s way from the AY.
Sum Up
It’s interesting to note the similarities between this and the final CPC design. As mentioned earlier the case had already been designed so clearly the connector layout would be similar but we also see the same (or very similar) choices for the key chips – 8255, AY-3 and 6845, and the AY-3 accessed via the 8255. The use of an 8255 in particular is interesting as it’s an Intel chip which uses ‘8080’ style control signals. Many 6502 designs use a MOS6522 for similar functionality.
As to the actual design itself it’s clear there’s not much on this board that would have worked in the way intended. They didn’t even manage to get a working CPU and ROM, let alone all the complex parts of the design. But this still leaves interesting questions. PCB layout is difficult with modern tools, forty years ago it was much harder. Was the problem here a failure to take a half-decent schematic and turn it into a PCB? Are those traces missing traces because they didn’t have the necessary skills to route them?
Taking a step back from the PCB, did they not wire-wrap the design first? Wire wrapping was the standard way to prototype circuits in that era. Faster and cheaper to create than a PCB and easier to modify. But if they had a working, or near working wire wrapped design then it’s likely Amstrad would have given them support to get the design finished, so that sounds unlikely.
Did they write any firmware or have plans to write any, or where they leaving that to someone else? The Rev 0, as with the CPC, has 32k of ROM, which requires a lot of software to fill.
It’s a shame there’s not enough here to tell us about the capabilities of the machine. Of course, we can see what it could do in terms of audio and I/O abilities, but what about video modes and colour depth, processor speed and whole system performance?
And would this machine have been a success in the market? The CPC was launched with a lot of third party software already available and an official magazine, official software (and hardware) vendor (Amsoft) and a user club. Oh, and a host of very good documentation. As I understand the story most of that was a result of suggestions by the development team (outside of Amstrad). Without the team that created the CPC Amstrad with the Rev 0 may well have been yet another short lived footnote in the history of 8-bit computing.
Perhaps it’s not fair to be too critical of the machine. According to The Register the two designers claimed they could finish the design in a month and collapsed with stress when they realised Amstrad expected them to make good on that claim. If so this is the result of a months very hasty development work. If they’d had longer could they have done better? We will, of course, never know.
Links
Amstrad CPC mainboard revisions on CPCWiki
“You’re NOT fired: The story of Amstrad’s amazing CPC 464” on The Register
Footnotes
- Or column select, depending on how you want to phrase things.
- I don’t know the 6502 well enough to say if this makes any sense, I suspect not.
- All the glue logic is 74LS series except where noted. I normally shorten part numbers for brevity.
- Thereby selecting a region of the 6502’s address space for I/O and generating device I/O selects for sub-sections of that I/O space.
- There are actually nine ‘X’ lines on the ‘464 keyboard but X8 and X9 are shorted together on the motherboard. I assume they left options for expanded keyboards in future but later keyboards reduced this to only eight lines.