In 2020 I began a project to emulate the gate array from an Amstrad CPC computer using a Raspberry Pi RP2040 IC (as used in the first generation RPi Pico microcontroller boards). The project ran into challenges due to insufficient GPIO pins on the chips and the need to convert voltage levels for signals between the CPC and the RP2040.

As I write this a second generation chip, the RP2350, has just been released. The new chip has 48 GPIO pins and those pins are 5V tolerant, which removes the need to level conversion, at least for signals from the CPC to the gate array . Thus I am now resurrecting the Pico Garry project with the updated name of ‘Pico Garry 2350’.

Articles in this series are intended more as public designed notes. Compared to my more in depth articles they are more ‘off-the-cuff’, less error checked, and design ideas within them may be obsoleted as the design evolves. You have been warned.

In this article I do some analysis of the signals used and generated by the Amstrad gate array. For a more in depth discussion of the signals used by the RAM and video subsystem see my in depth article.

As a quick summary, the gate array is driven by a 16MHz clock and runs through a 16 step cycle with each step occupying one cycle of the 16MHz clock. I refer to this as the ‘gate array cycle’.

In the following I divide the signals into groups for convenient reference and summarise the purpose of each signal, from the perspective of the gate array (ie. they may have other meanings elsewhere).

Z80SSIGS – Signals from the Z80

The following input signals are generated (usually) by the Z80 and are read by the gate array.

• D0 to D7: Video data bus, input only.
• A15: Address line, used to generate /ROMEN and /RAMRD.
• A14: Address line, used for I/O port decoding and for generating /ROMEN and /RAMRD.
• /RD: Memory or I/O read. Also used to infer /WR (write) during memory and I/O accesses.
• /MREQ: Memory read or write.
• /IORQ: I/O access (ie. writing to the gate array registers) and interrupt acknowledge.
• /M1: Interrupt acknowledge.

FSIGS – Fixed signals

The following output signals are generated on a fixed cycle.

• PHI: 4MHz system clock.
• /CCLK: Address line zero for video memory access, and clock for the 6845 CRTC.
• /CPU: Switches the multiplexers between CPU and video addresses. Also used as the 1MHz clock for the sound generator.
• /CASAD: Switches the multiplexers between RAS and CAS addresses.
• /RAS: Row address select to RAM.
• READY: /WAIT signal to the CPU and latch control (IC114) for data from RAM destined for the CPU.

CSIGS – Conditional signals

The following output signals vary depending on one of the Z80SIGS inputs. The conditional operation only happens during a fixed section of the gate array cycle.

• /MWE: Memory write enable. Only generated if /RD is high during the CPU part of the cycle.
• /CAS: Column address select for RAM. Has a fixed sequence during the video part of the cycle. Conditional on /MREQ during the CPU part of the cycle.
• /244EN: Enables data on the CPU data bus to pass to the video data bus (IC115). Necessary when the CPU is writing data to the gate array registers. The gate array actually generates this signal during all I/O requests, ignoring the read/write and I/O port statuses. This signal is only generated if /IORQ is active.

MEM – Memory read control

These signals are generate when reading from memory and depend on the state of the gate array’s ROM enable register, address lines A15 and A14, and /MREQ and /RD.

• /ROMEN: Read from ROM.
• /RAMRD: Read from RAM.

VIN – Video in

These signals are generated by the 6845 CRTC and control generation of the video output.

• DISPEN: Display enable. Asserted during the ‘pixel generation’ section of each scan row (not asserted during horizontal and vertical refresh, or when the ‘border’ is shown).
• VSYNC: Vertical sync (between each half frame).
• HSYNC: Horizontal sync (between each scan line).

VOUT – Video out

The following are generated by the gate array as the output video signal:

• R: Red channel.
• G: Green cannel.
• B: Blue channel.
• /SYNC: vertical and horizontal sync.

The gate array can generate three signal levels on each of the colour channels: high, low, and HiZ (tristate). My current plan is to use three pins for each colour channel. This will enable the display to use 512 colour values, which can be used to select a pallet which accurately matches that of the original machine, but could also be used to create new video modes.

Miscellaneous signals

• XTAL: 16MHz system clock.
• /INTERRUPT: Interrupt signal to the CPU.
• /RESET: System reset input.